This invention is based on and claims priority of Japanese patent application 2001-374515, filed on Dec. 7, 2001, the whole contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, relates to a semiconductor device which comprises a plurality of repeating units, each repeating unit being composed of a plurality of memory cells and a well tap for applying a constant voltage to a well in which MOS transistors constituting the memory cells are formed.
2. Description of the Related Art
In FIG. 10A, a plan view of a static random access memory cell (SRAM cell) disclosed in Japanese Unexamined Patent Application Publication No.8-181225 is shown. In FIG. 10B, a cross-sectional view taken along the line B10xe2x80x94B10 in FIG. 10A is shown.
Active regions 500 and 501 are defined by an element isolation insulation film 505. The active region 500 is provided in a p-type well 502, and the active region 501 is provided in an n-type well 503. As shown in FIG. 1A, the active 500 comprises a first portion 500a which extends in the lateral direction in the figure, and a second portion 500b and third portion 500c, which extend downward in the figure from the ends of the first portion 500a. 
The active region 501 has a long shape in the lateral direction in the figure. Two gate electrodes 506 and 507 extend in the longitudinal direction in the figure and intersect the first portion 500a of the active region 500 and the active region 501. At the intersection area between the active region 500 and the gate electrode 506, a pulldown MOS transistor Tr1 is formed, and at the intersection area between the active region 500 and the gate electrode 507, a pulldown MOS transistor Tr2 is formed. At the intersection area between the active region 501 and the gate electrode 506, a pullup MOS transistor Tr5 is formed, and at the intersection area between the active region 501 and the gate electrode 507, a pullup MOS transistor Tr6 is formed.
A word line 508 extends in the lateral direction in the figure and intersects the second portion 500b and the third portion 500c of the active region 500. At the intersection area between the second portion 500b and the word line 508, a transfer MOS transistor Tr3 is formed, and at the intersection area between the third portion 500c and the word line 508, a transfer MOS transistor Tr4 is formed.
In the active region 501, between the gate electrodes 506 and 507, a p-type source region 510 is provided for the pullup transistors Tr5 and Tr6. In the active region 500, between the gate electrodes 506 and 507, an n-type source region 511 is provided for the pulldown transistors Tr1 and Tr2.
In a part of the active region 501 between the gate electrodes 506 and 507, an n+-type well contact region 512 is formed. In a part of the active region 500 between the gate electrodes 506 and 507, a p+-type well contact region 513 is formed. The n+-type well contact region 512 is in contact with the p-type source region 510 (batting contact), and the p+-type well contact region 513 is in contact with the n-type source region 511 (batting contact).
A power supply voltage Vcc is applied to the n-type well 503 via the n+-type well contact region 512. A ground voltage Vss is applied to the p-type well 502 via the p+-type well contact region 513.
In order to normally operate the pulldown MOS transistors Tr1 and Tr2, an n-type impurity doped in the n+-type well contact region 512 must not to be doped in the vicinities of the gate electrodes 506 and 507. Doping of the impurity in the n+-type well contact region 512 is performed by ion implantation using a resist pattern having an opening corresponding to the n+-type well contact region 512.
In order to secure an alignment allowance when this resist pattern is formed, it is necessary that the n+-type well contact region 512 be provided at a predetermined distance from the gate electrodes 506 and 507 which are disposed at both sides of the n+-type well contact region 512. In a manner similar to the above, it is necessary that the P+-type well contact region 513 be provided at a predetermined distance from the gate electrodes 506 and 507 which are disposed at both sides of the P+-type well contact region 513.
For example, when the gate length is a generation of 0.13 xcexcm, the distance between the gate electrode 506 and the gate electrode 507 becomes 0.7 xcexcm. In this structure, the lateral width of one memory cell is approximately 1.55 xcexcm. On the other hand, when the well contact regions 512 and 513 are not provided, the distance between the gate electrodes 506 and 507 can be decreased to 0.35 xcexcm. In the above structure, the lateral width of one memory cell is 1.2 xcexcm. When the well contact regions 512 and 513 are provided between the gate electrodes, the area of the memory cell is increased by approximately 29%.
In FIG. 11, a plan view of a conventional SRAM in which the memory cell area can be decreased is shown. Four memory cells 600a to 600d are disposed in the lateral direction in the figure to form one memory cell array 600. A plurality of the memory cell arrays 600 is repeatedly disposed in the lateral direction and in the longitudinal direction in the figure, and between adjacent memory cell arrays in the lateral direction, a connection portion 605 is secured.
Each of the memory cells 600a to 600d comprises two pulldown MOS transistors Tr1 and Tr2, two pullup MOS transistors Tr5 and Tr6, and two transfer MOS transistors Tr3 and Tr4. In the memory cells 600a to 600d, well contact regions are not provided.
A p-type well 601 and an n-type well 602 are provided to extend in the lateral direction in the figure. In the p-type well 601, n-channel MOS transistors of the memory cells are formed, and in the n-well 602, p-channel MOS transistors are formed. A word line 606 is provided to extend in the lateral direction in the figure and is also used as gate electrodes of the transfer MOS transistors Tr3 and Tr4.
In the p-type well 601 and the n-type well 602 in the connection portion 605, a p-type well tap region 610 and an n-type well tap region 611 are provided, respectively. In the connection portion 605, a via hole 614 is provided for connecting the word line 606 to a main word line provided thereabove.
In FIG. 12, a cross-sectional view taken along the chain line A12xe2x80x94A12 in FIG. 11 is shown. The p-type well tap region 610 is connected to an intermediate conductive layer 623 via a conductive material filled in a via hole 612 formed in an interlayer insulating film 620. The intermediate conductive layer 623 is further connected to a ground voltage line which is provided thereon.
The n-type well tap region 611 is connected to an intermediate conductive layer 622 via the conductive material filled in a via hole 613 formed in the interlayer insulating film 620. The intermediate conductive layer 622 is further connected to a power supply voltage line which is provided above. The word line 606 is connected to an intermediate conductive layer 621 via the conductive material filled in a via hole 614 formed in the interlayer insulating film 620. The intermediate conductive layer 621 is connected to a main word line provided thereabove. In general, the main word line is formed of a metal, and as a result, an effective electrical resistance of the word line 606 formed of polycrystalline silicon is decreased.
In the conventional SRAM shown in FIGS. 11 and 12, well tap regions are not provided in individual memory cells, and in the connection portion 605 provided for every four memory cells, the well tap regions are provided. Accordingly, the areas of the well tap regions per one memory cell can be decreased.
FIG. 13 shows an enlarged plan view of the connection portion 605 of the conventional SRAM shown in FIG. 11. At the right side and the left side of the n-type well tap region 611 in the figure, a source region 630 of the pullup MOS transistor Tr5 of the memory cell disposed at one end of a memory cell array and a source region 631 of a pullup MOS transistor Tr6 of the memory cell disposed at one end of a memory cell array opposite to the memory cell array mentioned above with respect to the n-type well tap region 611 are provided, respectively.
Above the n-type well tap region 611, the intermediate conductive layer 622 is provided. Above the drain regions 630 and 631, intermediate conductive layers 632 and 633 are provided, respectively. The distance D between the intermediate conductive layers 622 and 632 adjacent to each other and the distance D between the intermediate conductive layers 622 and 633 are set to the minimum dimension used for patterning a wire layer of the semiconductor device.
The width of the connection portion 605 is restricted by the distance D which is set to the minimum dimension. In particular, the source region 630 of the pullup MOS transistor Tr5 of the memory cell array and the source region 631 of the pullup MOS transistor Tr6 of the memory cell array, which are opposite to each other with respect to the connection portion 605, must be provided apart from each other at a distance of at least two times the minimum dimension.
When the gate length is a generation of 0.13 xcexcm, the lateral width of the memory cell is approximately 1.2 xcexcm, and the width of the connection portion is approximately 1 xcexcm. When one connection portion is provided for every four memory cells, the effective lateral width of one memory cell is 1.45 xcexcm in consideration of the connection portion.
Accordingly, an object of the present invention is to increase the degree of integration of a semiconductor device in which a plurality of circuits such as memory cells, which are substantially equivalent to each other, are provided repeatedly.
A semiconductor device according to one aspect of the present invention comprises a plurality of repeating units repeatedly provided on a surface of a semiconductor substrate in a first direction and a second direction crossing to the first direction, each repeating unit comprising a plurality of memory cells, each memory cell comprising at least one first-conductivity-type channel MOS transistor having a first-conductivity-type source region, a first-conductivity-type drain region, and a gate electrode; a second-conductivity-type well provided in a surface layer of the semiconductor substrate, the second-conductivity type well extending over the plurality of the repeating units disposed in the first direction, the first-conductivity-type channel MOS transistor of each memory cell being provided on the second-conductivity-type well; a second-conductivity-type well tap region provided in one of the plurality of the memory cells in each repeating unit and in the second-conductivity-type well; an interlayer insulating film covering the surface of the semiconductor substrate; and a first interlayer connection member which is provided in the memory cell having the second-conductivity-type well tap region in each repeating unit or in the memory cell adjacent thereto and which penetrates the interlayer insulating film, the first interlayer connection member being connected to at least the source region of one of the first-conductivity-type channel MOS transistors of the memory cell in which the first interlayer connection member is provided and to the second-conductivity-type well tap region.
A constant voltage is applied to the source region of a first-conductivity-type MOS transistor and the second-conductivity-type well tap region via the first interlayer connection member. Since an interlayer connection member exclusively used for the well tap region is not necessary, the degree of integration of the semiconductor device can be increased.
As described above, the interlayer connection member for applying a constant voltage to the well tap region is also used as an interlayer connection member for applying a constant voltage to the source region of a MOS transistor adjacent to the well tap region. Accordingly, the interlayer connection member exclusively used for the well tap region is not necessary, and as a result, the degree of integration of the semiconductor can be increased.